The need for high speed and low latency cluster interconnect scheme for data and information transport between systems have been recognized as one needing attention in recent times. The growth of interconnected and distributed processing schemes have made it essential that high speed interconnect schemes be defined and established to provide the speed up the processing and data sharing between these systems.
There are interconnect schemes that allow data transfer at high speeds, the most common and fast one existing today is the Ethernet connection allowing transport speeds from 10 MB to as high as 10 GB/sec. TCP/IP protocols used with Ethernet have high over head with inherent latency that make it unsuitable for some distributed applications. Effort is under way in different areas of data transport to reduce the latency of the interconnect as this is a limitation on growth of the distributed computing power.
What is Proposed
PCI Express (PCIE) is an emerging I/O interconnect standard for use inside computers, or embedded systems that allow serial high speed data transfer to and from peripheral devices. The typical PCIE provides 2.5 GB transfer rate per link (this may change as the standard and data rates change). Since the PCIE standard is starting become firm and used within the systems, what is disclosed is the use of PCIE standard based peripheral to PCIE standard based peripheral connected directly using data links, as an interconnect between individual stand alone systems, typically through an interconnect module or a network switch. This interconnect scheme by using only PCIE based protocols for data transfer over direct physical connection links between the PCIE based peripheral devices, (see FIG. 1), with out any intermediate conversion of the transmitted data stream to other data transmission protocols or encapsulation of the transmitted data stream within other data transmission protocols, reduces the latencies of communication in a cluster. The PCIE standard based peripheral at a peripheral end point of the system, by directly connecting using PCIE standard based peripheral to PCIE standard based peripheral direct data link connections to the PCIE standard based peripheral at the switch, provides for increase in the number of links per connection as band width needs increase and thereby allow scaling of the band width available within any single interconnect or the system of interconnects.
Some Advantages of the Proposed Connection Scheme:
                1. Reduced Latency of Data transfer as conversion from PCIE to other protocols like ethernet is avoided during transfer.        2. The number of links per connection can scale from X1 to larger numbers X32 or even X64 possible based on the bandwidth needed.        3. Minimum change in interconnect architecture is needed with increased bandwidth, enabling easy scaling with need.        4. Standardization of the PCIE based peripheral will make components easily available from multiple vendors, making the implementation of interconnect scheme easier and cheaper.        5. The PCIE based peripheral to PCIE based peripheral links in connections allow ease of software control and provide reliable bandwidth.        